The present invention relates to an apparatus and method for at least semi-selectively depositing a material on a substrate by chemical vapor deposition. More particularly, the present invention relates to filling high aspect ratio vias, holes and contacts in a substrate by deposition of a metal interconnect layer.
In integrated circuit fabrication, electrically conductive, metal-containing material is deposited onto substrates to form interconnect lines and/or fill contact holes and vias, which are used to electrically connect active devices formed on substrates. The metal-containing interconnect lines are typically formed by sequentially (I) depositing layers of electromigration, diffusion barrier, electrical conductor, and/or antireflective materials, on the substrate, (ii) forming a patterned resist layer on the deposited layers, and (iii) etching the unprotected portions of the deposited layers to form the interconnect lines. An electrical insulator layer, such as silicon dioxide, is deposited over the interconnect lines to electrically isolate the interconnect lines. Contact holes or vias are etched through the insulator layer to expose underlying interconnect lines, or to expose semiconductor devices such as gates. The contact holes or vias are filled with additional metal-containing material to form plugs that connect the devices and interconnect lines formed on the substrate.
Conventional chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques are used to deposit electrically conductive material into the contact holes and vias formed on the substrate. One problem with conventional processes arises because the contact holes or vias comprise high aspect ratios, i.e., the ratio of the height of the holes to their width or diameter is greater than 1. The aspect ratio of the holes increases as advances in technology yield more closely spaced features.
Referring to FIG. 1, a substrate 10 comprises a hole 11 formed within an electrically insulative or dielectric layer 12, such as for example, silicon dioxide or silicon nitride. It is difficult to deposit a uniform metal-containing layer 13 into the high aspect ratio hole 11 using chemical vapor deposition processes because the metal-containing layer 13 often preferentially deposits on the sidewalls 14 of the holes and across the width of the hole to eventually converge and form voids and discontinuities 15 within the metal-containing material 13. Thereafter, the high mobility of metal atoms, such as aluminum atoms, surrounding the voids causes the atoms to diffuse and minimize the surface area of the voids forming circular shaped voids 15 as shown in FIG. 1. These voids and discontinuities 15 result in poor and unreliable electrical contacts.
One traditional CVD method used to fill contact holes and vias is selective CVD, wherein the chemical vapor nucleates, i.e., the deposition process begins at selected nucleation sites on the wafer. The usefulness of selective chemical vapor deposition of Al or other metals is limited due to the inability to effectively clean the via interface during a pre-cleaning step. SiO2 deposited in the via bottom inhibits selective nucleation and selective CVD metal via fill. This loss of selectivity results in a corresponding formation of a void inside the via and a drop in via yield. As aspect ratios increase, the via Ar+ flux, or other pre-clean flux, reaching the via bottom decreases, thereby reducing the effectiveness of sputter etch removal of Al2O3 which typically forms on the substrate surface when the substrate is exposed to ambient conditions. To effectively remove the Al2O3, longer etch times are required which decreases throughput of substrates in the system. In addition, as the etch times are increased, the fraction of material sputtered from the via corner increases proportionally as does the resulting SiO2 sputter flux deposition onto the via interface.
Liner processes have been developed to resolve the limitations of the selective CVD process. A liner, such as titanium (Ti) or titanium nitride (TiN), is deposited on a patterned substrate to provide a nucleation layer and a wetting layer over which deposition can proceed. The liner process overcomes limitations of the selective process by reducing the oxide interface at the via bottom with a thin layer of sputtered Ti or TiN. However, selectivity is lost since the Ti or TiN is also deposited on the via sidewall and substrate field surfaces. Therefore, selective CVD cannot be used to fill the aperture, so a thin conformal CVD Al is deposited into the aperture to form a liner. The Al liner is then covered with a PVD metal layer, such as aluminum. The substrate 10 is then heated to reflow temperatures causing the deposited aluminum to flow into the bottom of the contact holes and/or vias. However, because the PVD aluminum layer is only deposited on portions of the substrate 10 due to the limitations imposed by very small geometries, the layer must be heated to temperatures of about 400xc2x0 C. to about 550xc2x0 C., in order to provide a sufficiently low viscosity metal layer that flows into the holes 11 in the substrate 10. Such high temperatures limit the PVD and reflow techniques to only those where the substrates are not damaged by the high temperatures. For example, temperatures above 400xc2x0 C. can cause diffusion of dopant material and/or decomposition of the substrate. New generations of ever miniaturized integrated circuits require low processing temperatures to obtain the required levels of miniaturization, and to allow use of low temperature materials that are often unstable at temperatures exceeding 400xc2x0 C. In addition, as the aspect ratio increases, the thermal budget and resulting throughput is decreased. While the liner integration sequence provides cost, thermal budget and throughput improvements compared to traditional hot AlCu processing, it is still expensive relative to a selective sequence.
Conventional PVD methods, such as sputtering, also have problems that result because material sputtered off a sputtering target by energetic plasma ions travels to the substrate 10 in a relatively straight-line path to deposit primarily on those portions of the substrate within line-of-sight of the target. The line-of-sight deposition makes it difficult to fill high aspect ratio contact holes or vias that have an aspect ratio exceeding 1. Often, less than 5% of the material deposited by conventional PVD processes is formed within the holes 11, the remaining deposits being formed on top of the features adjacent to the holes 11.
Another problem with conventional deposition processes arises because such methods deposit crystalline grains 16 having random crystalline orientation which negatively affect electromigration performance. Highly oriented crystals, on the other hand, can reduce electromigration of the atoms within the crystal. Electromigration is a diffusive process in which atoms diffuse from one region to another region within the deposited layer under the influence of electrical fields across the substrate, causing voids that result in xe2x80x9copenxe2x80x9d junctions and unreliable electrical conductivity. Conductive layers having a highly oriented crystalline structure exhibit reduced electromigration of atoms, because in certain crystallographic orientations, the conductive layers have lower diffusion coefficients. For example, deposited aluminum grains that are highly oriented in the crystallographic plane having  less than 111 greater than  miller indices are found to exhibit excellent resistance to electromigratory diffusion. However, conventional deposition processes typically deposit more randomly oriented crystalline grains 16 on the substrate. This limits the current density that a conductive plug or interconnect line can carry to typically about 106 A/cm2, beyond which excessive electromigration would occur.
The randomly oriented crystalline grains provided by conventional CVD and PVD processes can also result in deposition of layers having non-planar surfaces, which is undesirable for modern VLSI circuits that use multiple layers of submicron sized features to form high speed circuits. The surface 17 of the filled holes 11 in such circuits need to be planar and flat in order to accurately fabricate high density miniaturized features using conventional photolithographic processes. Conventional CVD deposition processes form a deposition layer having irregular ridges 18 on features adjacent to the holes 11 that result in an uneven and irregular surface 17, as shown in FIG. 1. The uneven deposition layers produce unfocussed or blurred resist patterns in the photo lithographic process, and on being etched, provide features having irregular line widths.
Thus, there is a need for a process for filling high aspect ratio contact holes and vias in a substrate with metal-containing material, without forming voids or defects in the deposited material. It is also desirable for the deposition process to deposit grains that are highly oriented in particular crystallographic planes.
The present invention provides a chemical vapor deposition process for at least semi-selectively depositing a substantially planar, highly reflective layer on a substrate, and is particularly useful for filling high aspect ratio holes formed on the substrate. A patterned substrate having a conductive or semi-conductive barrier layer formed thereon is positioned in a process zone, and an insulating layer is preferentially deposited on the field of the substrate. In one embodiment, the insulating layer is deposited by introducing nitrogen (N2) and dimethyl aluminum hydride (DMAH) into the process zone to preferentially deposit a layer of AlN on the field of the substrate to the exclusion of the contact holes and vias. Thereafter, a metal layer is selectively deposited in the contact holes and vias using CVD processes. Preferably, a thin, self-aligning nucleation layer is deposited on the field of the substrate over the insulating film to provide controlled deposition on the field of the substrate so that deposition on the field proceeds at a slower rate than deposition in the contact holes and vias. Alternatively, a warm metal layer, preferably  greater than 250xc2x0 C., may be deposited on the CVD metal layer to overcome the selectivity loss on the field by depositing a blanket layer on the field. In addition, AlCu or other doped material may be deposited over the CVD metal layer to allow migration of the Cu or other dopant throughout the metal layer.
Other insulating layers may be preferentially deposited and may comprise materials such as SiN, TiO2, combinations thereof, or any other insulating material which can be deposited on the field of a substrate. Further, while Al is a preferred CVD metal layer, Cu or any other CVD metal may be semi-selectively deposited in the contact holes or vias.
Another aspect of the present invention includes the control system for operating a process chamber for depositing a substantially planar, highly reflective layer on the substrate. The computer product comprises a computer usable medium having computer readable program code means. The computer code means comprises:
(a) substrate positioning code for positioning the substrate in the chamber,
(b) heater control code for operating a heater; and
(c) process gas control for (I) in an insulating deposition mode, introducing one or more reactive gases into the process zone to preferentially deposit an insulating film, and (ii) in a subsequent selective deposition mode, introducing one or more deposition gases into the process zone to selectively deposit a metal-containing layer.